Semiconductor Engineering

RTL Design-for-Power In Mobile SoCs

If you are one of the more than 2 billion smartphone users today, it is hard to imagine life without one! Breaking new frontiers, wearable smart devices and the Internet of things are the latest buzz.
Nasdaq

Synopsys Unveils RTL Architect To Accelerate Design Closure

The RTL Architect product represents the industry's first physically aware RTL analysis, optimization, and signoff system built on a fast, multi-dimensional prediction engine for superior RTL handoff ...
EDN

Exploring new design flows — RTL synthesis

Editor's Note: In Part 2 of this series,consultant and ASIC designer Tom Moxoncovered several trends in virtual silicon prototying design flows.In this installment of the series he'll show how to link ...
Design-Reuse

Siemens launches Tessent tool for Verilog and RTL design for test

The Tessent RTL Pro enables analysis and insertion of a large majority of their DFT logic very early in the design flow, performing quick synthesis and then running ATPG (automatic test pattern ...
EDN

Book Review: Principles of VLSI RTL Design – A Practical Guide by Sanjay Churiwala and Sapan Garg

Generally speaking, there are only so many books I can read on RTL design before my eyes start to glaze over. Having said this, there’s the occasional gem that’s well worth a read, such as Principles ...
Semiconductor Engineering

RTL Design-for-Power (DFP) Methodology

Commercial power analysis tools have been available now for over 10 years, operating at the gate and transistor level of abstraction. For analog, mixed-signal, and custom designs, transistor-level ...
Embedded

Demonstrations show HDL RTL reuse in ESL design

LONDON Tenison Design Automation is demonstrating how its VTOC works with the ARM RealView SoC Designer with MaxSim technology, to incorporate existing RTL into new SystemC ESL designs. VTOC is ...
Electronic Design

Startup Aims To Automate RTL Closure Process

Rising design complexity causes innumerable headaches in achieving functional design closure. Startup firm Blue Pearl Software plans to address design closure at RTL using a combination of design-rule ...
Electronic Design

A flexible flow for inserting embedded compression logic in RTL

The standard approach for testing IC logic is the use of scan chains, with embedded compression as the standard approach for applying scan patterns. Embedded compression enables the same test quality ...