IEEE

High Performance Image Processing: Comparative Analysis of FPGA and ASIC Hardware Accelerations

Abstract: The study mainly focuses on Gaussian convolution for image smoothing and XOR based encryption for security, implemented on FPGA (ZCU104 using Vivado) and ASIC (Cadence Innovus at 45nm). The ...
IEEE

HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineers

Abstract: Recently, the use of large language models (LLMs) for Verilog code generation has attracted great research interest to enable hardware design automation. However, previous works have shown a ...
GitHub

Pull requests: bindhuanuhya/Project-on-Bus-Ticketing-System-using-Verilog-HDL

Pull requests help you collaborate on code with other people. As pull requests are created, they’ll appear here in a searchable and filterable list. To get started, you should create a pull request.
GitHub

A subset of RISC-V architecture (RV32I) implementation for low-resource FPGA

A tiny version of RISC-V for low-resource FPGA developed by the Integrated System Design lab, School of Electronics, KIIT University Objective The main objective of this project is to prototype a RISC ...