EDN

Layout compaction accelerates SoC design through hard IP reuse

In enabling multimillion-gate SoC designs, the latest process technologies have widened the gap between manufacturing capabilities and designers' abilities to quickly put together these complex ...
Electronic Design

Optimize SoC Design with a Network-on-Chip Strategy

How third-party interconnect IP saves time, lowers risk, and speeds completion. NoC is the predominant SoC interconnect strategy. NoC IP accommodates multiple interconnect protocols and data widths.
EDN

SoC design: What’s next for NoCs?

Today’s high-end system-on-chips (SoCs) rely heavily on sophisticated network-on-chip (NoC) technology to achieve performance and scalability. As the demands of artificial intelligence (AI), ...
Electronic Design

Functional Safety for Control and Status Registers

Today's SoCs include hundreds of complex IP blocks with millions of transistors each. CSRs are essential for managing these IPs, with some systems having up to a million CSRs. IP-XACT standards help ...