Business Wire

Aldec Brings Assertions to FPGA Designers with the Release of Active-HDL 8.1

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-language simulation for ASIC and FPGA devices, announced today the release of Active-HDL 8.1. The new release introduces a ...
Design-Reuse

Aldec's Active-HDL Verification Capabilities Enhanced to Support SystemVerilog Constructs and UVM

Henderson, USA – December 3, 2019 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification ...
Business Wire

Aldec Releases Active-HDL 10.1 with 64-bit Simulation Support

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., announces the latest release of its mixed-language FPGA design platform, Active-HDL™ 10.1. Popular with designers for more than 15 years for FPGA design ...
EDN

Link for Modelsim 2 adds direct Verilog support

SAN FRANCISCO — The MathWorks Monday (July 24) announced the availability of Link for ModelSim 2, said to enhance the use of model-based design for hardware verification by offering full Verilog and ...
Design-Reuse

InterMotion Technology boosts IP verification productivity for Lattice Semiconductor's CrossLink FPGA family using Aldec's Active-HDL

Henderson NV, USA – March 24, 2020 – Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, today announced that InterMotion Technology ...